1. Field of the Invention
The invention relates to a dynamic type semiconductor memory device such as dynamic random access memory (DRAM), and more particularly to a dynamic type semiconductor memory device including a sense-amplifier having a function of compensating for a threshold value, and being capable of storing a plurality of bit data in a single memory cell.
2. Description of the Related Art
In these days, many techniques have been developed in order to enhance integration and capacity in a dynamic type semiconductor memory device. For instance, Japanese Unexamined Patent Publication No. 3-16049 has suggested a memory device including three devices, that is, two transistors and one capacitor having the same storage capacitance as that of a conventional one, and storing two-bit data. Namely, one bit corresponds to 1.5 devices in this memory device.
FIG. 1 is a circuit diagram of a circuit constituting the semiconductor memory device suggested in the above-mentioned Japanese Unexamined Patent Publication No. 3-16049, FIG. 2 illustrates waveforms of input signals in the circuit illustrated in FIG. 1, and FIGS. 3 and 4 illustrate waveforms of a voltage found when a bit line is to be read.
As illustrated in FIG. 1, the illustrated circuit includes a memory cell 20 having two transistors and one capacitor to store two-bit data therein, a storage capacitor 21, transfer gates 23 and 24 connected in series to the storage capacitor 21 for reading data stored in the storage capacitor 21 onto a bit line, and storage nodes 24 and 25. The circuit also includes two sense-amplifiers 26 and 27 in parallel.
Hereinbelow is explained an operation of the circuit illustrated in FIG. 1, with reference to FIG. 2 illustrating input timing waveforms.
With reference to FIG. 2, when bit line equalizing control signals NEQ and PEQ varies in such a fashion as illustrated in FIG. 2 at time t0, all transistors in a bit line equalizing circuit are turned off, and pre-charging of the bit line is completed. As a result, voltages across the transistors become Vcc/2.
Then, supposing that a memory cell 20 to which bit lines BLL1 and /BLL1 are electrically connected is selected, CUT2 turns off a transistor electrically connected to CUT2 of a separation circuit of the bit line sense-amplifier, and rises up a word line WLL1 at time t1. Herein, a symbol "/" means a complementary signal. For instance, "/BLL1" indicates a complementary signal of the signal BLL1.
As a result, data stored in the storage capacitor 21 is charge-transferred to the bit lines BLL1, BLR1, SBL1, SBL2 and /BLL1, /BLR1, /SBL1, and /SBL2.
Then, when signals CUT1 and REQ are fallen down at time t2, a bit line located at the same side of the memory cell 20 is separated from the sense-amplifier 26, and SBL1 and SBL2 are separated from /SBL1 and /SBL2. Thus, the sense-amplifiers 26 and 27 individually stores the same data transmitted from the memory cell 20.
After UP and DOWN signals have been altered in such a manner as illustrated in FIG. 2 at time t3, an operation of sense amplification caused by /SAS begins at time t4, and CUT1 and CUT2 are risen up at time t5 to thereby electrically connect the sense amplifier to a bit line located at the same side of the memory cell 20. Thus, there is carried out pull-up by /SAS.
Finally, CSEL is fallen down at time t6 to thereby transfer amplified data of the memory cell 20 into a data line. Thus, a reading operation is completed.
Since the above-mentioned memory cell 2 in the conventional circuit stores two-bit data in a single storage capacitor, there are four statuses of voltages across the storage nodes 24 and 25 when the memory cell stores data, as shown in Table 1. The term "Data" in Table 1 indicates data to be output to data lines D1 and D2. "H" corresponds to Vcc, and "L" corresponds to GND voltage.
TABLE 1 ______________________________________ D1 = H D1 = H D1 = L D1 = L Data D2 = H D2 = L D2 = H D2 = L ______________________________________ Node 14 Vcc 2 Vcc/3 Vcc/3 GND Node 15 GND Vcc/3 2 Vcc/3 Vcc ______________________________________
FIG. 3 illustrates a status found when data D1=H and D2=H are to be read out, and FIG. 4 illustrates a status found when data D1=H and D2=L are to be read out.
As illustrated in FIG. 3, when data D1=H and D2=H are to be read out, there is generated a voltage difference .DELTA.V between complementary bit lines at time t1 at which a word line rises up. At time t3, voltages of SBL1 and /SBL2 are risen by .DELTA.V/3, whereas voltages of /SBL1 and SBL2 are decreased by .DELTA.V/3, due to UP and DOWN signals.
However, without voltages of SBL1 and /SBL1 and voltages of SBL2 and /SBL2 being not reversed, Vcc level voltages are output through the data lines D1 and D2 after operation of sense-amplification has been conducted at time T4.
When data D1=H and D2=L are to be read out, as illustrated in FIG. 4, there is generated only a voltage difference .DELTA.V/3 in each of complementary bit line pairs at time t1 at which word lines rise up. Thus, voltages of SBL1 and /SBL2 are increased by .DELTA.V/3 by virtue of signals UP and DOWN at time t3. When voltages of /SBL1 and SBL2 are decreased by .DELTA.V/3, voltages of SBL2 and /SBL2 are reversed. Accordingly, after operation of sense-amplification has been conducted at time t4, the voltage Vcc is output to the data line D1, and GND level is output to the data line D2.
However, since the above-mentioned conventional semiconductor memory device has a memory cell structure comprising two transistors and one capacitor, it is unavoidable that a memory cell has a complex structure and a method of fabricating the same is complicated in comparison with a general dynamic random access memory (RAM) having a memory cell structure comprising one transistor and one capacitor.
In addition, it is necessary in the above-mentioned conventional semiconductor memory device to draw wirings from opposite electrodes of a capacitor to complementary bit lines through two transistors. Hence, if higher integration would be attempted, it would be difficult to layout a memory device with symmetry being maintained in a structure, which would cause a problem of degradation in margin such as reading margin.